Skip to article frontmatterSkip to article content
Site not loading correctly?

This may be due to an incorrect BASE_URL configuration. See the MyST Documentation for reference.

1Learning Outcomes

Can we be more efficient in writing sequential C code on a serial processor? We discussed some optimizations in an earlier section. We can write assembly code and do better with “micro” optimizations like loop unrolling—but in general, compilers are pretty good nowadays and it’s not that easy to beat them. We can rewrite our programs to make better use of the memory hierarchy, like we explored with our cache blocking exercise earlier.

But how do we leverage hardware improvements? That is the topic of this section.

2Parallelism: Software vs. Hardware

Because of the abrupt shift in processor design towards parallelism, there are a LOT of closely related terms when it comes to paralellism. Table 1 is an adaptaion of P&H 6.1 to clarify the terms used in software versus hardware.

Table 1:Software perspective on concurrency vs. hardware perspective on parallelism.

Software
HardwareSequentialConcurrent
SerialBasic matrix multiply running on single-core systemOperating System running on single-core system
ParallelBasic matrix multiply running on modern laptopOperating System running on modern laptop

Notes:

The last of these points is the most important.

3Flynn’s Taxonomy

Now let’s shift towards classifying serial and parallel hardware using Flynn’s Taxonomy.[1] There are four entries in Table 2 that classify different levels of parallelism based on data streams and instruction streams.

Table 2:Flynn’s taxonomy: A system for classifying parallel hardware.

Data Streams
Instruction StreamsSingleMultiple
SingleSISDSIMD
MultipleMISDMIMD

Toggle the tabs below to discover examples of each type of architecture.

SISD
SISD Uses
"Flynn taxonomy SISD diagram with a data pool on the left and an instruction pool on the top that both feed into a processor unit box in the center."

Figure 1:SISD: Single Instruction/Single Data Stream

SIMD
SIMD Uses
"Flynn taxonomy SIMD diagram a data pool on the left that feeds into four parallel processor unit boxes in the center. A single instruction pool at the top similarly feeds into the four parallel processor units."

Figure 2:SIMD: Single Instruction/Multiple Data Stream

MISD
MISD Uses
"Flynn taxonomy MISD diagram with a single stream data pool that feeds into one processor unit and then the other, and an instruction pool that feeds into both processor units in parallel."

Figure 3:MISD: Multiple Instruction/Single Data Stream

MIMD
MIMD Uses
"Flynn taxonomy MIMD diagram with a data pool that feeds four streams of data through four parallel processor units and then another four parallel processor units, and an instruction pool that feeds the first set of processor units in parallel and the second set of four processor units in parallel with a second instruction stream."

Figure 4:MIMD: Multiple Instruction/Multiple Data Stream

Over the next few lectures, we will explore these architectures and write programs that exploit the hardware parallelism available. Stay tuned!!!

Footnotes
  1. Professor Michael J. Flynn was Professor Emeritus at Stanford University. In 1962, he proposed a taxonomy of computer architectures. Flynn’s taxonomy is still used today to describe modern processors. Wikipedia

  2. For what it’s worth, most programs written today assume a SPMD (single program, multiple data) model. With SPMD, we write a single program that uses multiple degrees of parallelism across processors of a MIMD computer with some cross-processor coordination.